IEEE

A Robust FPGA Router With Optimization of High-Fanout Nets and Intra-CLB Connections

Abstract: Routing is the most time-consuming step in the implementation flow of field programmable gate array (FPGA) designs. With the advance in transistor scaling and system integration, hardware ...
CNX Software

AMD VEK385 Versal AI Edge Gen 2 FPGA evaluation kit plugs directly into a PCIe Gen5/Gen4 slot

AMD has introduced the VEK385 Evaluation Kit built around the Versal AI Edge Gen 2 XC2VE3858 SoC FPGA, which combines eight Cortex-A78AE cores, ten Cortex-R52 cores, FPGA fabric with 543,104 LUTs, 144 ...
IEEE

FPGA IP Core for DC Motor Control With Adaptive Neural Network PID Tuning, and High-Resolution Encoder Interface

Abstract: Traditional proportional integral derivative (PID) falls short for precise control of DC motor speed under changing conditions. This paper presents a novel FPGA based IP (intellectual ...
GitHub

FPGA Capstone: Building FPGA Projects

In this project, I designed a mixed-signal system that measures voltage using the Analog-to-Digital Converter (ADC) and controls an output using a Pulse Width Modulation (PWM) circuit. Quartus Prime's ...