Design And Reuse

QuickLogic Announces New Seven-Figure FPGA Hard IP Contract

QuickLogic Corporation (NASDAQ: QUIK), a developer of embedded FPGA (eFPGA) Hard IP, Strategic Radiation Hardened and Antifuse FPGAs, and ruggedized programmable solutions, announced today it has been ...
Design And Reuse

SiFive Sets New Bar for High-Performance RISC-V with Third-Generation Performance P550 and P570 IP

New high-performance OoO superscalar vector processor IP, ideal for area- and power-constrained consumer applications SiFive, Inc., the gold standard for RISC-V computing, today announced the launch ...
Design And Reuse

Siemens democratizes EDA software access for European electronics industry through the Chips JU European Chips Design Platform (EuroCDP) project

Siemens has become the first software provider to sign a strategic framework agreement with the European Chips Joint Undertaking (Chips JU) which aims to bolster Europe's semicond ...
Design And Reuse

CEA-Leti Platform Offers Chipmakers Nanometre- Scale Strain Mapping

Strain engineering, which involves deliberately stretching or compressing a crystal lattice, is used to boost the speed of electron flow in a device. Even a fraction of percent change in lattice ...
Design And Reuse

LTSCT Expands Advanced Power Design Capabilities with Synopsys

L&T Semiconductor Technologies Ltd (LTSCT), a leading Indian fabless semiconductor company and a wholly-owned subsidiary of Larsen & Toubro (L&T), today announced a multiyear license agreement with ...
Design And Reuse

Apple-Intel Foundry Deal Could Reshape U.S. Chip Manufacturing

If realized at a meaningful scale, the partnership could reshape the economics of advanced semiconductor manufacturing, accelerate the transformation of Intel Foundry, and test the increasingly ...
Design And Reuse

HighTec EDV-Systeme and SiFive: Together strengthening the RISC-V Ecosystem for Safe and Secure Automotive and Industrial Applications

SiFive’s automotive-focused RISC-V processor IP delivers scalable performance with built-in support for functional safety and security requirements. Designed for safety-critical automotive and ...
Design And Reuse

Ceva Advances Full-Stack Wireless Vision with Next Generation Bluetooth High Data Throughput and Integrated RF Design Win

(NASDAQ: CEVA), the leading licensor of silicon and software IP for the Smart Edge, today announced a major customer win for its Bluetooth® High Data Throughput (HDT) solution including Ceva’s ...
Design And Reuse

EXTOLL announces Availability of Industry´s first 16G UCIe PHY IP in GlobalFoundries 22FDX/22FDX+ Ready for Customer Integration

EXTOLL, a leading provider of high-speed and ultra-low-power SerDes and Chiplet connectivity, announces the availability and readiness for customer integration of the industry´s first 16G UCIe PHY IP ...
Design And Reuse

Chips&Media Completes Development of Next-Gen 'AV2' HW Decoder IP

HW RTL release in May with active commercial licensing talks underway with major North American clients ...
Design And Reuse

Aeva Adopts Cadence Tensilica Vision DSP to Advance Lidar Performance and Efficiency

Cadence (Nasdaq: CDNS) today announced that Aeva, a leader in next-generation sensing and perception systems, has licensed Cadence ® Tensilica ® Vision DSP IP to accelerate signal processing in its 4D ...
Design And Reuse

SEMIFIVE and ICY Tech Achieve Successful Tape-out of 8nm eMRAM-Based Edge AI SoC, Targeting First Commercialization in Asia

This collaboration represents SEMIFIVE's first ASIC design project leveraging eMRAM technology. By integrating eMRAM into an Edge AI accelerator, the company aims to reinforce its technical leadership ...